During the formation of semiconductor devices, it is often necessary to electrically couple layers which are vertically arranged. That is, it is often necessary to electrically couple features on one layer to features on an underlying or an overlying layer. In order to accomplish such a task, an opening is typically formed extending through the vertically arranged layers. The contact opening is then filled with a conductive material so as to form a conductive path extending between the vertically arranged layers.
Prior Art FIG. 1A shows a side sectional view of a conventional semiconductor device structure 100. In Prior Art FIG. 1A, a substrate, not shown, has a polysilicon gate structure 102 formed thereover. Lightly doped drain (LDD) spacer oxide structures, typically shown as 104a and 104b are disposed on the sides of polysilicon gate structure 102. The conventional structure of Prior Art FIG. 1A further includes a nitride layer 106 which is disposed thereover.
Referring still to Prior Art FIG. 1A, a high density plasma (HDP) deposited oxide layer 108 is disposed overlying nitride layer 106. Next, a cap oxide layer 110 formed, for example, of silicon dioxide is disposed over HDP layer 108. In Prior Art FIG. 1A, semiconductor device structure 100 is shown after a planarization process has been performed to provide a smoothly planarized top surface.
Referring next to Prior Art FIG. 1B, an opening 112 is shown formed extending through portions of cap oxide layer 110 and underlying HDP layer 108. As shown in Prior Art FIG. 1B, the bottom portion or "etch-front" of opening 112 is substantially flat (i.e. horizontally oriented and parallel to the top surface of semiconductor device structure 100). The etch-front can be thought of as the patterned oxide surface which is undergoing ion bombardment and reactive etching during the progression of the etch. During the formation and location of opening 112, misalignments frequently occur. That is, instead of locating and forming opening 112 directly over a source or drain region, a portion of opening 112 can be formed overlying LDD spacer oxide 104b, as shown in Prior Art FIG. 1B. When such a misalignment occurs, an edge/corner of the etch-front of opening 112 can contact nitride layer 106 overlying LDD spacer oxide 104b.
Referring now to Prior Art FIG. 1C, another example of a misaligned opening 112 is shown. In the example of Prior Art Fig. 1C, instead of locating and forming opening 112 directly over polysilicon gate structure 102 as desired, a portion of opening 112 is shown inadvertently formed overlying LDD spacer oxide 104a. When such a misalignment occurs, an edge/corner 116 of the etch-front of opening 112 can contact nitride layer 106 overlying LDD spacer oxide 104a.
Referring again to Prior Art FIG. 1B, due to the above-described misalignment (i.e. edge 114 of the etch-front of opening 112 overlying LDD spacer oxide 104b), nitride layer 106 may be deleteriously etched during the formation of opening 112. That is, even though it intended to etch only through cap oxide layer 110 and HDP oxide layer 108 and stop at the portion of nitride layer 106 overlying the source/drain region, conventional contact opening formation methods may result in unwanted etching of nitride layer 106 overlying the LDD spacer oxide. This problem associated with the prior art is further exacerbated by the fact that nitride layer 106 is deposited nonconformally over LDD spacer oxide 106. Thus, the portion of nitride layer 106 residing along the edge of LDD spacer oxide 104b is typically thinner than the portion of nitride layer 106 residing above the source/drain region. Additionally, during the timed progression of the etch, the etch-front of opening 112 reaches the sloped edge along the side of LDD spacer oxide 104b before the etch-front reaches the portion of nitride layer 106 overlying the source/drain region. As a result, the nitride along the edge of LDD spacer oxide 104b is potentially subjected to a longer etch time than is the portion of nitride layer 106 overlying the source/drain region. As yet another substantial drawback, sputtering efficiency is greater when the surface being etched is at some angle other than normal to the impinging ions, with peak efficiency occurring at 45 degrees. Therefore, the portion of nitride layer 106 residing along the edge of LDD spacer oxide 104b etches much faster than would any portion of the nitride layer which is parallel to the etch-front of opening 112 (e.g. the portion of nitride layer 106 residing above the source/drain region).
With reference now to Prior Art FIG. 1D, a deleterious condition associated with the misalignment of Prior Art FIG. 1B is shown. Specifically, for the reasons mentioned above, a portion of nitride layer 106 residing along the edge of LDD spacer oxide 104b has been etched away. As a result, the LDD spacer oxide 104b has also been etched and severely compromised. Thus, in such prior art methods, instead of forming an opening extending through cap oxide layer 110 and HDP oxide layer 108 to the top surface of nitride layer 106 above the source/drain region as intended, it is possible that the LDD spacer oxide 104b is damaged.
The preceding discussion specifically describes defects associated with a misalignment occurring when attempting to form opening 112 over a source/drain region. It will be understood, however, that similar defects are associated with a misalignment occurring when attempting to form opening 112 over a polysilicon gate structure (see e.g. Prior Art FIG. 1C).
Thus, a need exists for a semiconductor device structure which enhances process margin by preventing unwanted etching of various features during the formation of a contact opening. A further need exists for a semiconductor device structure which meets the above need without requiring substantial deviation from existing semiconductor manufacturing steps and processes.